1. Field of the Invention
The present invention relates to a cache memory, a processor having a cache memory and a production technique thereof.
2. Description of the Related Art
A capacity of a cache memory built in a processor has been on the increase in recent years due to requirements for better performance, so has been a probability of a whole processor failing due to a failure in the cache memory.
In the meantime, it has been in demand to reduce varieties of product for cost reduction, it is meaningful to reduce the number of products practically by salvaging a processor failed due to a faulty cache memory with a substitution operation and thereby shipping out the processor as a lower grade processor having a smaller cache memory.
Meanwhile, produced LSI's such as processors are unit-tested before shipping. The unit test, also called a function test, is for confirming an LSI to function electrically according to the design data thereof, such as whether it operates as per the functions on a tester, logically correct, et cetera.
For example, a RAM as a component of a built-in processor cache memory usually has a self test circuit therein, by which a RBIST (Ram_Built_In_Self_Test)-J (hereinafter called “self test”) is performed for testing the function of READ and WRITE for each RAM, and the result is reported as FAIL information. A redundant bit is built into a RAM for every plurality of bits which relieves a failed part thereof by substituting for the faulty bit (faulty cell array) in response to the FAIL information. The substitution is usually done using a FUSE programmable by a laser or the like. That is, a sound cell array is put into function in place of the faulty cell array by cutting the fuse (FUSE cut).
Subsequently, if the self test is conducted again, the result shall yield a pass since the faulty part has been substituted, and as such the product is successfully shipped out as a perfect “pass.” However, if failed in the substitution, or if there is a manufacturing problem in RAM such as a fault in the redundant bits for substitution, a repeated FAIL will result. The RAM is accordingly diagnosed as a “fail.” This is a way in which an LSI whose built-in RAM is found to be faulty by the unit test is determined as to whether or not usable as a “semi-pass” LSI having a smaller cache memory capacity.
In conventional techniques, however, since the information on RAM substitution obtained for each LSI had to be managed and set from outside the LSI, the substitution of a failed RAM with a sound RAM has been difficult in the actual operation and hence practically impossible.
For this reason, it is conceivable, for instance, to classify RAMs in two large groups and use simply a certain group of RAMs for usage modes requiring small cache memory capacities, thereby picking out the semi-passes.
In that case, however, if there is a faulty RAM in the group from which a RAM is to be selected for use, the LSI cannot secure a desired number of RAMs and hence being discarded.
As noted above, if a substitution operation is to be done on an individual RAM basis based on the substitution information on the sound and failed RAMs for each LSI obtained by a screening test, the information on the RAM substitution obtained for each LSI has conventionally to be managed and set from outside the LSI, and hence there has been no practical method available for the substitution of a sound RAM for a failed RAM.
Note that in the patent document 1 listed below, a technique is disclosed in which a faulty data address of a cache memory is set in the tag RAM of the aforementioned cache memory and, if the faulty data address is accessed, a “miss” in a hit/miss judgment is reported to the microprocessor and thereby inhibiting an access to the faulty data in the aforementioned cache memory.
Meanwhile, in the patent document 2, a technique for an LSI, such as a processor, consisting of a plurality of functional blocks is disclosed in which a partial-pass is shipped out by selectively blocking out the functional block where a failure is detected.
Meanwhile, in the patent document 3, a technique is disclosed in which the cache memory address where a parity error occurred is degraded to a lower access priority, thereby improving the overall cache memory performance.
As such, since all techniques disclosed in the patent documents 1 through 3 either isolate an error part or inhibit an access thereto, they do not contribute to a yield of cache memories by taking advantage of the aforementioned cache memories having a redundant configuration, or of processors having such a cache memory.    [Patent document 1] Japanese patent laid open application publication 7-182238    [Patent document 2] Japanese patent laid open application publication 2000-99361    [Patent document 3] Japanese patent laid open application publication 4-243446